Request for EG25-G firmware A0.301 package, release notes, and AUX PCM documentation

Technical Resources LTE Standard Module Resources
1

Hello Quectel team,

We are evaluating the Quectel EG25-G Mini PCIe module, hardware reference EG25GGB-MINIPCIE. The firmware identified by our supplier is:

EG25GGBR07A08M2G_A0.301.A0.301

Could you please provide, or direct us to the authorized channel for obtaining:

  1. The complete official firmware/recovery package for this exact build, with its SHA-256 checksum and applicable module/revision information.
  2. The release notes for A0.301, including changes relative to EG25GGBR07A08M2G_30.203.30.203.
  3. The PCM/AUXPCM documentation for this build.

Our specific question is whether bidirectional digital PCM audio on the module’s physical PCM pins is supported during an active VoLTE call, including RX and TX, without an external analog audio codec. We understand that VoLTE support, or the presence of PCM drivers and ALSA routes in firmware images, does not by itself demonstrate working audio on the physical pins.

If supported, please clarify the required pin configuration, clock and frame-sync settings, audio format, firmware configuration, and any initialization procedure or daemon required. Please also identify the appropriate hardware test procedure to verify both directions during a real call.

We have previously examined static images from 30.203; we have not established that A0.301 contains the same components or that either build provides functional physical-pin audio.

Thank you.

2

Hi @Rene_Garbi

Kindly check your email for the firmware and supporting documents.

EG25-G Mini PCIe Edge Connector Pinout

1. Digital PCM Audio Interface (1.8 V Logic)

  • Pin 45 ( PCM_CLK ): Bit clock signal (DIO)
  • Pin 47 ( PCM_DOUT ): PCM data output (DO)
  • Pin 49 ( PCM_DIN ): PCM data input (DI)
  • Pin 51 ( PCM_SYNC ): Frame synchronization signal (DIO)

2. I2C Interface (1.8 V Logic)

  • Pin 30 ( I2C_SCL ): Serial Clock (OD) - Requires an external pull-up resistor to 1.8 V
  • Pin 32 ( I2C_SDA ): Serial Data (OD) - Requires an external pull-up resistor to 1.8 V (If connecting directly to a host DSP without an analog codec, leave Pins 30 and 32 unconnected).

3. Firmware Configuration & AT Commands

  1. Configure PCM for Direct Digital Output: Execute AT+QDAI with =1 to enable defined digital PCM output:

    AT+QDAI=[io],[mode],[fsync],[clock],[format],[sample],[num_slots],[slot_mapping]

  2. Master Mode Example (2048 kHz BCLK, 8 kHz short frame sync, 16-bit linear PCM):

    AT+QDAI=1,1,0,4,0,0,1,1

  3. Slave Mode Example (Module accepts clock/sync from host/DSP):

    AT+QDAI=1,1,0,4,0,0,1,1
    (Note: AT+QDAI configurations take effect after rebooting the module).

  4. Enable PCM Clock Signal:

    AT+QCFG=“pcmclk”,1

  5. Verify IMS/VoLTE Registration: Ensure IMS/VoLTE functionality is enabled:

    AT+QCFG=“ims”,1

    Query status via AT+QCFG=“ims”; a response of +QCFG: “ims”,1,1 confirms VoLTE session availability.

4. Hardware Test Procedure During a Real Call

  1. Set AT+QDAI=1,… and AT+QCFG=“pcmclk”,1, then reboot the module
  2. Verify cellular registration (AT+CREG? / AT+CEREG?) and confirm IMS registration (AT+QCFG=“ims”).
  3. Place or answer a VoLTE voice call (ATD<phone_number>; or ATA).
  4. Use an oscilloscope or logic analyzer to probe Pin 27 (PCM_CLK) and Pin 26 (PCM_SYNC) to confirm clock signals match configured rates.
  5. Observe Pin 25 (PCM_OUT) during far-end speech to confirm active 16-bit PCM stream output.
  6. Inject a 16-bit linear PCM audio stream into Pin 24 (PCM_IN) synchronized to PCM_CLK and PCM_SYNC, then verify audio playback at the far-end receiver.