I’m trying to test “PSM in between eDRX cycles” on a Cat-M network with a BG95-M3 flashed with FW BG95M3LAR02A03.
- AT+QPTWEDRXS=2,4,“0001”,“0101” (e-I-DRX enabled with e-I-DRX=81.92s and PTW=2.56s) and I see network confirming these parameters after registration; tried also with longer e-I-DRX cycle, but same result
- AT+QPSMCFG=20,12 (so with Bit3 - “PSM in between eDRX cycles” of <PSM_version> enabled)
- AT+QSCLK=1 and DTR set to OFF
Module does not enter lowest power state (less than 10 uA expected) during e-I-DRX cycles, out of PTW. Am I missing something in the configuration?
Just to note, I can see “normal” PSM working as expected (with e-I-DRX disabled).