EC25 QuecOpen MAIN UART HW flow control

hi all
is there in QuecOpen HW flow control?
i need rs485 communication and trying these variants:

1. use linux rules to hw flow control via RTS pin:

 int fd_uart = open(UART1_DEV, O_RDWR);

if (fd_uart<0) {
printf(“UART1 open error”);

struct serial_rs485 ctrl485;
ctrl485.flags |= SER_RS485_ENABLED;
ctrl485.flags &= ~(SER_RS485_RTS_ON_SEND);
ctrl485.flags |= SER_RS485_RTS_AFTER_SEND;
if (ioctl(fd_uart, TIOCSRS485, &ctrl485) < 0) {
printf(“Error %i initializing rs485: %s\n”, errno, strerror(errno));

i have a error 25: Inappropriate ioctl for device.

2. use QuecOpen Library with an GPIO output to flow control a RS485 ic:

		Ql_GPIO_SetLevel(m_GpioPin, PINLEVEL_LOW);
		iRet = Ql_UART_Write(fd_uart, uartBuf, uartBufSize);
		Ql_GPIO_SetLevel(m_GpioPin, PINLEVEL_HIGH);

but on the pins i have this image:

i have these quections:

  1. how i can configure MAIN UART as RS-485 port?
  2. can i see implementation of int Ql_UART_IoCtl(int fd, unsigned int cmd, void* pValue);
    or examples?
  3. only timeouts can resolve my problem?

Hi Denis_Syrf
Copy the msm.c to the kernel directory ql-ol-kernel/drivers/tty/serial, and recompile and update the kernel. (28.8 KB)
The following is the test application. The test is OK on EC25EFAR06A02, where rs485conf.padding[3] = 11; the control pin is configured, 11 is the GPIO port number of Qualcomm SOC, and the pin corresponding to EC25 is pin 4.

1 Like

big thanks, FelixCheng-Q.
i maked a temporary solution with ic MAX22028AWA+ (RS-485 with auto-direction).
Now I am carrying out the next stage of work - LAN and Wifi.
I’m novice and i’m afraid to update the kernel because I don’t know the specifics of doing this under QuecOpen. if you can - specify please the features of kernel update on QuecOpen. Or specify the manual to study this issue.
I mean that to recompiling i need use these commands:

source ../ql-ol-crosstool/ql-ol-crosstool-env-init

After completing work on the main project, I will definitely implement the possibility of using any half-duplex ICs.
sorry for my bad english.
regards from Russia

Please follow the instructions I gave you. Quectel has verified that it is feasible. Big thanks