Hello @silvia
Quectel
RM505Q-AE
Revision: RM505QAEAAR11A03M4G
at+qnwcfg=?
+QNWCFG: “lte_cdrx”,(0,1),(0,1)
+QNWCFG: “nr5g_cdrx”,(0,1)
+QNWCFG: “csi_ctrl”,(0,1),(0,1)
+QNWCFG: “lte_csi”
+QNWCFG: “nr5g_csi”
+QNWCFG: “lte_cell_id”
+QNWCFG: “nr5g_cell_id”
+QNWCFG: “lte_csi_ext”,(0,1)
+QNWCFG: “nr5g_csi_ext”,(0,1)
+QNWCFG: “lte_tx_pwr”,(0,1)
+QNWCFG: “nr5g_tx_pwr”,(0,1)
+QNWCFG: “wcdma_cqi”
+QNWCFG: “up/down”,(1-60)
+QNWCFG: “data_path”,(0,1)
+QNWCFG: “dss_enable”,(0,1)
+QNWCFG: “lte_dl_tx_mode”
+QNWCFG: “nr5g_ulMCS”,(0,1)
+QNWCFG: “nr5g_dlMCS”,(0,1)
+QNWCFG: “nr5g_pusch_data”,(0,1)
+QNWCFG: “lapi”,(0,1)
+QNWCFG: “nr5g_meas_info”,(0,1)
+QNWCFG: “lte_time_advance”,(0,1)
+QNWCFG: “nr5g_time_advance”,(0,1)
+QNWCFG: “clr_rplmn”
+QNWCFG: “dis_rplmnact”,(0,1)
+QNWCFG: “lte_ambr”
+QNWCFG: “nr5g_ambr”
+QNWCFG: “dis_4mimo_enable”,(0,1)
+QNWCFG: “nr5g_ulTBsize”,(0,1),(1-100)
+QNWCFG: “encryp_alg_support”
+QNWCFG: “integ_alg_support”
+QNWCFG: “data_roaming”,(0,1)
+QNWCFG: “nr5g_earfcn_lock”,(0-32),earfcn1:scs1:…:earfcnN:scsN
+QNWCFG: “lte_earfcn_lock”,(0,1),earfcn1:earfcn2
+QNWCFG: “event_a3_offset”,(0,1),(0-255)
+QNWCFG: “used_algo”,(0,1)
+QNWCFG: “nr5g_pref_freq_list”,(0-32),earfcn1:scs1:…:earfcnN:scsN
+QNWCFG: “lte_pref_freq_list”,(0-32),earfcn1:…:earfcnN
+QNWCFG: “ehplmn_config”,(0-20),plmn1:plmn2:…:plmnN
+QNWCFG: “nr5g_mimo”,(0,1)
+QNWCFG: “ctrl_plane_dly”,(0,1)
+QNWCFG: “rrc_state”
+QNWCFG: “ssb_beam_id”,(0,1)
+QNWCFG: “ul_data_path”,(0,1)
+QNWCFG: “lte_ulMCS”,(0,1)
+QNWCFG: “lte_mimo_layers”
+QNWCFG: “nr5g_mimo_layer”,(0,1)
+QNWCFG: “lte_band_priority”,
+QNWCFG: “cause7_map_cause14”,(0,1)