Bring up RM520-GL on NVIDIA Jetson platform

Hi
I have a RM520NGLAA‑M20‑SGASA 5G module(pcie interface)
I’m trying to bring it up on NVIDIA Jetson AGX Orin platform
I have a driver provided by Quectel(pcie_mhi_adpl_qdss_v1.3.4)

[  819.472260] mhi_init Quectel_Linux_PCIE_MHI_Driver_V1.3.4
[  819.472808] mhi_q 0000:01:00.0: Adding to iommu group 56
[  819.473028] mhi_pci_probe pci_dev->name = 0000:01:00.0, domain=0, bus=1, slot=0, vendor=17CB, device=0308
[  819.473820] mhi_q 0000:01:00.0: BAR 0: assigned [mem 0x2728000000-0x2728000fff 64bit]
[  819.475212] mhi_q 0000:01:00.0: enabling device (0000 -> 0002)
[  819.476060] [I][mhi0][mhi_init_pci_dev] msi_required = 6, msi_allocated = 6, msi_irq = 302
[  819.476087] [I][mhi0][mhi_power_up] dev_state:RESET
[  819.476093] [I][mhi0][mhi_async_power_up] Requested to power on
[  819.476223] [I][mhi0][mhi_alloc_coherent] size = 147456, dma_handle = fffc0000
[  819.476229] [I][mhi0][mhi_init_dev_ctxt] mhi_ctxt->ctrl_seg = 00000000de96ed4e
[  819.476564] [I][mhi0][mhi_async_power_up] dev_state:RESET ee:AMSS
[  819.476587] [I][mhi0][mhi_pm_st_worker] Transition to state:READY
[  819.476603] [I][mhi0][mhi_pm_st_worker] INVALID_EE -> AMSS
[  819.476607] [I][mhi0][mhi_ready_state_transition] Waiting to enter READY state
[  819.476676] [I][mhi0][mhi_async_power_up] Power on setup success
[  819.476777] [I][mhi0][mhi_pci_show_link] LnkCap:     Speed 16GT/s, Width x2
[  819.476781] [I][mhi0][mhi_pci_show_link] LnkSta:     Speed 8GT/s, Width x1
[  819.476783] [I][mhi0][mhi_pci_probe] Return successful
[  822.496291] [I][mhi0][mhi_ready_state_transition] Device in READY State
[  822.496336] [I][mhi0][mhi_tryset_pm_state] Transition to pm state from:POR to:POR
[  822.496358] [I][mhi0][mhi_init_mmio] Initializing MMIO
[  822.496370] [I][mhi0][mhi_init_mmio] CHDBOFF:0x300
[  822.496388] [I][mhi0][mhi_init_mmio] ERDBOFF:0x700
[  822.496395] [I][mhi0][mhi_init_mmio] Programming all MMIO values.

Probe message shows success, but nothing comes further.
From the SDX55 PCIE bring-up document, I think something is not complete or went wrong


but in my device there is no such node under /dev

gemtek@tegra-ubuntu:/home$ ls /dev/mhi*
/dev/mhi_BHI

and using quectel-CM

gemtek@tegra-ubuntu:/home$ sudo ./quectel-CM 
[12-10_02:05:36:389] QConnectManager_Linux_V1.6.2
[12-10_02:05:36:390] network interface '' or qmidev '' is not exist
[12-10_02:05:36:390] qmidevice_detect failed
[12-10_02:05:36:390] atdevice_detect failed
[12-10_02:05:36:390] qmidevice_detect failed

can’t open anything

Any idea what’s going on here?

Kevin

Please test with the lastest pcie_mhi driver.
Typically such issues are caused by an incorrect power-up sequence.

What’s the Linux kernel version. Can you show the lspci -v

Hi, Bean
My Linux version will be 5.15.148-tegra
Where can I get the latest pcie_mhi driver
and here is the lspci -v result

0000:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1) (prog-if 00 [Normal decode])
        Flags: bus master, fast devsel, latency 0, IRQ 204, IOMMU group 56
        Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
        I/O behind bridge: [disabled]
        Memory behind bridge: 40000000-400fffff [size=1M]
        Prefetchable memory behind bridge: [disabled]
        Capabilities: <access denied>
        Kernel driver in use: pcieport
        Kernel modules: tegra_pcie_dma_test

0000:01:00.0 Unassigned class [ff00]: Qualcomm Device 0308
        Subsystem: Qualcomm Device 5201
        Flags: bus master, fast devsel, latency 0, IRQ 302, IOMMU group 56
        Memory at 2728000000 (64-bit, non-prefetchable) [size=4K]
        Memory at 2728001000 (64-bit, non-prefetchable) [size=4K]
        Capabilities: <access denied>
        Kernel driver in use: mhi_q

0007:00:00.0 PCI bridge: NVIDIA Corporation Device 229a (rev a1) (prog-if 00 [Normal decode])
        Flags: bus master, fast devsel, latency 0, IRQ 208, IOMMU group 59
        Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
        I/O behind bridge: 00000000-00000fff [size=4K]
        Memory behind bridge: 40000000-400fffff [size=1M]
        Prefetchable memory behind bridge: [disabled]
        Capabilities: <access denied>
        Kernel driver in use: pcieport
        Kernel modules: tegra_pcie_dma_test

0007:01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)
        Flags: bus master, fast devsel, latency 0, IRQ 208, IOMMU group 59
        Memory at 3228000000 (32-bit, non-prefetchable) [size=512K]
        I/O ports at 400000 [disabled] [size=32]
        Memory at 3228080000 (32-bit, non-prefetchable) [size=16K]
        Capabilities: <access denied>
        Kernel driver in use: igb

Thanks

Please try the Quectel_Linux_PCIE_MHI_Driver_V1.3.8.zip.

Hi Bean
The results are the same

[26896.285436] mhi_init Quectel_Linux_PCIE_MHI_Driver_V1.3.8
[26896.308968] mhi_pci_probe pci_dev->name = 0000:01:00.0, domain=0, bus=1, slot=0, vendor=17CB, device=0308
[26896.309232] [I][mhi0][mhi_arch_set_bus_request] Setting bus request to index 1
[26896.309247] mhi_q 0000:01:00.0: BAR 0: assigned [mem 0x2728000000-0x2728000fff 64bit]
[26896.309826] [I][mhi0][mhi_init_pci_dev] msi_required = 4, msi_allocated = 4, msi_irq = 302
[26896.309843] [I][mhi0][mhi_power_up] dev_state:RESET
[26896.309846] [I][mhi0][mhi_async_power_up] Requested to power on
[26896.309917] [I][mhi0][mhi_alloc_coherent] size = 98304, dma_handle = fffc0000
[26896.309921] [I][mhi0][mhi_init_dev_ctxt] mhi_ctxt->ctrl_seg = 00000000d87f1f65
[26896.310151] [I][mhi0][mhi_async_power_up] dev_state:RESET ee:PBL
[26896.310201] [I][mhi0][mhi_async_power_up] Power on setup success
[26896.310301] [I][mhi0][mhi_pci_show_link] LnkCap:     Speed 16GT/s, Width x2
[26896.310303] [I][mhi0][mhi_pci_show_link] LnkSta:     Speed 8GT/s, Width x1
[26896.310305] [I][mhi0][mhi_pci_probe] Return successful

But I mark
rmnet_nss_callbacks function in the code since there are compilation errors
not sure if that affect anything

here is the result for sudo lspci -v with more detail

0000:01:00.0 Unassigned class [ff00]: Qualcomm Device 0308
        Subsystem: Qualcomm Device 5201
        Flags: bus master, fast devsel, latency 0, IRQ 302, IOMMU group 56
        Memory at 2728000000 (64-bit, non-prefetchable) [size=4K]
        Memory at 2728001000 (64-bit, non-prefetchable) [size=4K]
        Capabilities: [40] Power Management version 3
        Capabilities: [50] MSI: Enable+ Count=4/32 Maskable+ 64bit+
        Capabilities: [70] Express Endpoint, MSI 00
        Capabilities: [100] Advanced Error Reporting
        Capabilities: [148] Secondary PCI Express
        Capabilities: [168] Physical Layer 16.0 GT/s <?>
        Capabilities: [18c] Lane Margining at the Receiver <?>
        Capabilities: [19c] Transaction Processing Hints
        Capabilities: [228] Latency Tolerance Reporting
        Capabilities: [230] L1 PM Substates
        Capabilities: [240] Data Link Feature <?>
        Kernel driver in use: mhi_q

Thanks
Kevin

According to that it need the correct power-up sequence.

I thought if my device already recognized pcie device, the power-up sequence is correct.
Do I need a firmware to make it work?

Thanks
Kevin

It should be problem of the power-up sequence.
It is RM520NGLAA so only when the module boot into Linux kernel so that it can work as PCIe EP device.
I think you can try to power up the module in the bootloader.

Hi
After adding gpioset in UEFI to trigger 5G module on pin, the result is still the same, showing unassigned class
Here is the result measured with scope, it should match the time sequence from datasheet
(Weird is that there are two times Clkreq requests from the card)

yellow: pcie rst
light blue: clk req
pink: module on/off
dark blue: vcc

Can you give us some guide

Kevin


The PCIe RST must pull high after the wakeup pin signal. If the PCIe RST pull high too earlier or too late it would still fail.

Hi

yellow: pcie_rst
light_blue: clkreq
pink:module on/off
dark blue:pcie_wake
Can you tell us what is the criteria for these interval

Kevin

My current understanding is that PERST is first asserted in the bootloader, but this should actually be done in the kernel. The bootloader’s PCIe support is uncertain, so that code ought to be removed. From past experience, we can safely power the module in the bootloader and defer PERST until the kernel takes over.